1. Field of Invention
The present invention relates to a protection structure. More particularly, the present invention relates to an electrostatic discharge protection structure applied in semiconductor manufacturing processes.
2. Description of Related Art
Semiconductor manufacturers and electronic device users continue to demand faster, increasingly complex devices in smaller packages at lower costs. In order to meet those demands, semiconductor manufacturers keeps shrinking geometries of the devices. As the devices turn compact and clearances and line widths approach theoretical limits, devices are becoming increasingly susceptible to damage by electrostatic discharge (ESD). Short, fast, high-amplitude ESD pulses are an inevitable part of the daily environments of both chips and equipments. In fact, ESD is the leading cause of device failure in the field. The destructive mechanism associated with ESD in devices is primarily melting of the device material due to high temperatures. Due to the nature of ESD, it must be assumed that all devices will encounter an event during the normal course of their lifetime. Hence, ensuring that devices provide a reasonable and acceptable level of tolerance to ESD is an important part of all device design and manufacturing programs.
To determine the ESD threshold of a device, it is necessary to agree on the type of ESD stress for which testing will take place. There are presently three major ESD stress types: Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). For HBM, the threshold voltage can be as high as 2KV, while the threshold voltage for MM is around 200V. Electrostatic discharge, during manufacture, most commonly occurs at the input-output port on the circuit. Typically, an additional protection structure or circuit is designed to provide a discharge path for the additional current caused during electrostatic discharge, thus preventing damage to the device or the IC.
The incorporation of an ESD protection circuit into a deep-submicron MOS circuit is particularly difficult because the gate oxide layer is relatively thin in deep submicron fabrication. In addition, the breakdown voltage of the gate oxide layer is relatively low, about 10–20V. Therefore, triggering voltage of the ESD protection circuit must be lowered to a level below the breakdown voltage of the gate oxide layer in order to provide an effective protection.